revision 2.3 jan. 2004 1 a6 stc very low power/voltage cmos sram 32k x 8 bit power dissipation speed (ns) standby (i ccsb1 , max) operating (i cc , max) product family operating temperature vcc range vcc= 3.0v vcc= 5.0v vcc= 3.0v vcc= 5.0v vcc= 3.0v pkg type STC62WV256sc sop-28 STC62WV256tc tsop-28 STC62WV256pc pdip-28 STC62WV256jc soj-28 STC62WV256dc 0 o c to +70 o c 2.4v ~ 5.5v 70 1ua 0.2ua 35ma 20ma dice STC62WV256si sop-28 STC62WV256ti tsop-28 STC62WV256pi pdip-28 STC62WV256ji soj-28 STC62WV256di -40 o c to +85 o c 2.4v ~ 5.5v 70 2ua 0.4ua 40ma 25ma dice ? wide vcc operation voltage : 2.4v ~ 5.5v ? very low power consumption : vcc = 3.0v c-grade : 20ma (max.) operating current i- grade : 25ma (max.) operating current 0.01ua (typ.) cmos standby current vcc = 5.0v c-grade : 35ma (max.) operating current i- grade : 40ma (max.) operating current 0.4ua (typ.) cmos standby current ? high speed access time : -70 70ns (max.) at vcc=3.0v ? automatic power down when chip is deselected ? three state outputs and ttl compatible ? fully static operation ? data retention supply voltage as low as 1.5v ? easy expansion with ce and oe options the STC62WV256 is a high performance , very low power cmos static random access memory organized as 32,768 words by 8 bits and operates from a wide range of 2.4v to 5.5v supply voltage. advanced cmos technology and circuit techniques provide both high speed and low power features with a typical cmos standby current of 0.01ua and maximum access time of 70ns in 3v operation. easy memory expansion is provided by active low chip enable (ce), active low output enable (oe) and three-state output drivers. t he STC62WV256 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. the STC62WV256 is available in the dice form, jedec standard 28pin 330mil plastic sop, 300mil plastic soj, 600mil plastic dip and 8mm x 13.4mm tsop (normal type). ? description ? features ? block diagram ? product family ? pin configurations stc international limited . reserves the right to modi fy document contents without notice. address input buffer row decoder memory array 512 x 512 column i/o write driver sense amp column decoder data buffer output address input buffer a3 a2 a1 a0 a10 data buffer input control gnd vdd oe we ce dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 a12 a11 a9 a8 a7 a5 8 8 8 8 12 64 512 512 18 a14 a13 a4 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a10 ce dq7 dq6 dq5 dq4 dq3 gnd dq2 dq1 dq0 a0 a1 a2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 oe a11 a9 a8 a13 we vcc a14 a12 a7 a6 a5 a4 a3 STC62WV256 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd vcc we a13 a8 a9 a11 oe a10 ce dq7 dq6 dq5 dq4 dq3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ? ? r0201-STC62WV256 STC62WV256tc STC62WV256ti 62wv256sc 62wv256si 62wv256pc 62wv256pi 62wv256jc 62wv256ji .com .com .com
revision 2.3 jan. 2004 2 stc c in input capacitance v in =0v 6 pf c dq input/output capacitance v i/o =0v 8 pf ? absolute maximum ratings (1) ? operating range ? capacitance (1) (ta = 25 o c, f = 1.0 mhz) 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 1. this parameter is guaranteed and not 100% tested. symbol parameter rating units v term terminal voltage with respect to gnd -0.5 to vcc+0.5 v t bias temperature under bias -40 to +125 o c t stg storage temperature -60 to +150 o c p t power dissipation 1.0 w i out dc output current 20 ma STC62WV256 range ambient temperature vcc commercial 0 o c to +70 o c2.4v ~ 5.5v industrial -40 o c to +85 o c2.4v ~ 5.5v r0201-STC62WV256 name function a0-a14 address input these 15 address inputs select one of the 32768 x 8-bit words in the ram ce chip enable input ce is active low. chip enables must be active when data read from or write to the device. if chip enable is not active, the device is deselected and is in a standby power mode. the dq pins will be in the high impedance state when the device is deselected. we write enable input the write enable input is active low and controls read and write operations. with the chip selected, when we is high and oe is low, output data will be present on the dq pins; when we is low, the data present on the dq pins will be written into the selected memory location. oe output enable input the output enable input is active low. if the output enable is active while the chip is selected and the write enable is inactive, data will be present on the dq pins and they will be enabled. the dq pins will be in the high impedance state when oe is inactive. dq0 ? dq7 data input/output ports these 8 bi-directional ports are used to read data from or write data into the ram. vcc power supply gnd ground ? truth table ? pin descriptions mode we ce oe i/o operation vcc current not selected x h x high z i ccsb , i ccsb1 output disabled h l h high z i cc read h l l d out i cc write l l x d in i cc symbol parameter conditions max. unit .com .com .com .com
revision 2.3 jan. 2004 3 parameter name parameter test conditions min. typ. (1) max. units vcc=3.0v v il guaranteed input low voltage (2) vcc=5.0v -0.5 -- 0.8 v vcc=3.0v 2.0 v ih guaranteed input high voltage (2) vcc=5.0v 2.2 -- vcc+0.2 v i il input leakage current vcc = max, v in = 0v to vcc -- -- 1 ua i lo output leakage current vcc = max, ce = v ih , or oe = v ih , v i/o = 0v to vcc -- -- 1 ua vcc=3.0v v ol output low voltage vcc = max, i ol = 2ma vcc=5.0v -- -- 0.4 v vcc=3.0v v oh output high voltage vcc = min, i oh = -1ma vcc=5.0v 2.4 -- -- v vcc=3.0v -- -- 20 i cc operating power supply current ce = v il , i dq = 0ma, f = fmax (3) vcc=5.0v -- -- 35 ma vcc=3.0v -- -- 1 i ccsb standby current-ttl ce = v ih , i dq = 0ma vcc=5.0v -- -- 2 ma vcc=3.0v -- 0.01 0.2 i ccsb1 standby current-cmos ce R R Q R R Q R R Q .com .com .com .com
revision 2.3 jan. 2004 4 jedec parameter name parameter name description cycle time : 70ns min. typ. max. unit t avax t rc read cycle time 70 -- -- ns t avq v t aa address access time -- -- 70 ns t elqv t acs chip select access time -- -- 70 ns t glqv t oe output enable to output valid -- -- 50 ns t elqx t clz chip select to output low z 10 -- -- ns t glqx t olz output enable to output in low z 10 -- -- ns t ehqz t chz chip deselect to output in high z -- -- 35 ns t ghqz t ohz output disable to output in high z -- -- 30 ns t axox t oh data hold from address change 10 -- -- ns input pulse levels input rise and fall times input and output timing reference level vcc/0v 1v/ns 0.5vcc ? ac electrical characteristics ( ta =0 o c to + 70 o c and vcc=3.0v) read cycle ? ac test conditions ? ac test loads and waveforms ? key to switching waveforms waveform inputs outputs must be steady may change from h to l don t care: any change permitted does not apply must be steady will be change from h to l change : state unknown center line is high impedance ?off ?state may change from l to h will be change from l to h , stc STC62WV256 r0201-STC62WV256 ? ? ? ? ? .com .com .com .com
revision 2.3 jan. 2004 5 ? switching waveforms (read cycle) read cycle1 (1,2,4) t rc t oh t aa d out address t oh read cycle3 (1,4) read cycle2 (1,3,4) notes: 1. we is high in read cycle. 2. device is continuously selected when ce = v il . 3. address valid prior to or coincident with ce transition low. 4. oe = v il . 5. transition is measured 500mv from steady state with c l = 5pf as shown in figure 1b. the parameter is guaranteed but not 100% tested. stc STC62WV256 t clz t chz (5) d out ce (5) t acs t oh t rc t oe d out ce oe address t clz (5) t acs t chz (1,5) t ohz (5) t olz t aa r0201-STC62WV256 r .com .com .com .com
revision 2.3 jan. 2004 6 jedec parameter name parameter name description cycle time : 70ns min. typ. max. unit t avax t wc write cycle time 70 -- -- ns t e1lwh t cw chip select to end of write 70 -- -- ns t avw l t as address set up time 0 -- -- ns t avw h t aw address valid to end of write 70 -- -- ns t wlwh t wp write pulse width 50 -- -- ns t whax t wr write recovery time (ce , we) 0 -- -- ns t wloz t whz write to output in high z -- -- 30 ns t dvwh t dw data to write time overlap 40 -- -- ns t whdx t dh data hold from write time 0 -- -- ns t ghoz t ohz output disable to output in high z -- -- 30 ns t whqx t ow end ot write to output active 5 -- -- ns ? ac electrical characteristics ( ta =0 o c to + 70 o c and vcc=3.0v) write cycle stc STC62WV256 r0201-STC62WV256 write cycle1 (1) t wr (3) t cw (11) (2) t wp t aw t ohz (4,10) t as t dh t dw d in d out we ce oe address (5) t wc ? switching waveforms (write cycle) .com .com .com .com
revision 2.3 jan. 2004 7 write cycle2 (1,6) stc t wc t cw (11) (2) t wp t aw t whz (4,10) t as t dh t dw d in d out we ce address (5) t ow (7) (8) (8,9) STC62WV256 r0201-STC62WV256 notes: 1. we must be high during address transitions. 2. the internal write time of the memory is defined by the overlap of ce and we low. all signals must be active to initiate a write and any one signal can terminate a write by going inactive. the data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. t wr is measured from the earlier of ce or we going high at the end of write cycle. 4. during this period, dq pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. if the ce low transition occurs simultaneously with the we low transitions or after the we transition, output remain in a high impedance state. 6. oe is continuously low (oe = v il ). 7. d out is the same phase of write data of this write cycle. 8. d out is the read data of next address. 9. if ce is low during this period, dq pins are in the output state. then the data input signals of opposite phase to the outputs must not be applied to them. 10. transition is measured 500mv from steady state with c l = 5pf as shown in figure 1b. the parameter is guaranteed but not 100% tested. 11. t cw is measured from the later of ce going low to the end of write. r .com .com .com .com
revision 2.3 jan. 2004 8 ? ordering information stc STC62WV256 r0201-STC62WV256 ? package dimensions ? package dimensions t b base metal with plating c1 c b1 sop - 28 0.020 d 0.005x45 c note: stc (stc international limited.) assumes no responsibili ty for t he application or use o f a ny product or circuit described herei n. stc does n ot a uthorize its products for use as cr itical components in any application in which the failu re of the stc product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. package j: soj s: sop p: pdip t: tsop (8mm x 13.4mm) d: dice STC62WV256 x x y y grade c: +0 o c ~ +70 o c i: -40 o c ~ +85 o c speed 70: 70ns pkg material -: normal g: green p: pb free .com .com .com .com
revision 2.3 jan. 2004 9 ? package dimensions (continued) stc STC62WV256 r0201-STC62WV256 pdip - 28 1 14 14 d 1 hd c l 28 15 "a" 15 28 with plating section a-a base metal c c1 b1 b 12 c (2x) 12 (2x) a seating plane "a" datail view a1 a2 seating plane 12 c (2x) e b 12 c (2x) e gauge plane l1 l a a 0 0.254 y 0.004 ~ 0.006 0.004 ~ 0.008 0.0045 d 0.0026 0.0315 d 0.004 0.0197 0.022 d 0.004 0.008 d 0.001 0 c ~ 8 c 0.004 max. 0.528 d 0.008 0.315 d 0.004 0.465 d 0.004 0.009 d 0.002 0.039 d 0.002 0.0433 d 0.004 inch c1 l1 0 y d e hd l e symbol c a a1 b a2 b1 unit 0.10 ~ 0.16 0.80 d 0.10 0 c ~ 8 c 0.1 max. 0.55 d 0.10 11.80 d 0.10 0.50 13.40 d 0.20 8.00 d 0.10 - 0.004 +0.008 -0.10 +0.20 0.115 d 0.065 mm 0.10 ~ 0.21 0.20 d 0.03 0.22 d 0.05 1.00 d 0.05 1.10 d 0.10 tsop - 28 .com .com .com .com
revision 2.3 jan. 2004 10 stc STC62WV256 r0201-STC62WV256 ? package dimensions (continued) soj - 28 .com .com .com
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